As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
A capacitor is comprised of two conductive electrodes separated by a non-conducting dielectric layer. The dielectric layer is preferably comprised of one or more materials having a very high dielectric constant and low leakage current characteristics. Example materials include SiO.sub.2 and Si.sub.3 N.sub.4. Si.sub.3 N.sub.4 is typically preferred due to its better dielectric properties than SiO.sub.2. Numerous other capacitor dielectric materials have been and are being developed in an effort to meet the increasingly stringent requirements associated with the production of smaller and smaller capacitor devices used in higher density integrated circuitry. Most of these materials do, however, add increased process complexity or cost over utilization of conventional Si.sub.3 N.sub.4 and SiO.sub.2 capacitor dielectric materials. Yet the smaller and thinner capacitors being produced in next generation DRAM density are reaching the limit of the utility of using Si.sub.3 N.sub.4 as a viable capacitor dielectric material.
Specifically, Si.sub.3 N.sub.4 is typically deposited by low pressure chemical vapor deposition (i.e., any chemical vapor deposition process at less than or equal to 100 Torr). This does, however, undesirably produce very small pin-holes through thin layers of less than 200 Angstroms, with the pin-holes becoming particularly problematic in layers less than or equal to about 50 Angstroms thick. These pin-holes undesirably reduce film density and result in undesired leakage current in operation. Once developed, these leakage current inducing pin-holes are difficult to repair. One technique is to form the capacitor dielectric layer as a composite of a SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 composite. The strapping SiO.sub.2 layers is are utilized principally to cure or plug the pin-holes formed in the Si.sub.3 N.sub.4. Conventional circuitry today provides the SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 composite layer to thicknesses approaching 50 Angstroms. However, it is difficult at best to obtain thinner composite layers which achieve desirable dielectric film properties for such capacitor dielectric layers. Part of the difficulty in obtaining thinner composite layers is due to the SiO.sub.2 having a lower dielectric constant than Si.sub.3 N.sub.4. Accordingly, a capacitor dielectric construction having SiO.sub.2 must be thinner than a construction comprising only Si.sub.3 N.sub.4 to achieve an equal capacitance.
A semiconductor wafer fragment 10 comprising a prior art capacitor construction 14 is illustrated in FIG. 1. Wafer fragment 10 comprises a substrate 12. Substrate 12 can comprise, for example, a monocrystalline silicon wafer lightly doped with a p-type background dopant. To aid in interpretation of this disclosure and the claims that follow, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Capacitor assembly 14 is formed over substrate 12, and comprises a first capacitor electrode 16, a dielectric layer 18, and a second capacitor electrode 20. First capacitor electrode 16 and second capacitor electrode 20 can comprise, for example, conductively doped polysilicon, and can be formed by, for example, chemical vapor deposition. Dielectric layer 18 comprises the above-discussed SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 composite. The formation of dielectric layer 18 is illustrated in the expanded process views of FIG. 2 and FIG. 3.
Referring to FIG. 2, wafer fragment 10 is illustrated at a preliminary step in formation of capacitor construction 14 (shown in FIG. 1). A first SiO.sub.2 layer 22 has been formed over first cell electrode layer 16, and a silicon nitride layer 24 has been formed over first SiO.sub.2 layer 22. Silicon nitride layer 24 comprises a plurality of pinholes 26 extending into it. Some of pinholes 26 extend entirely through layer 24. Oxide layer 22 ensures that first capacitor electrode 16 is not exposed through any such pinholes 26 extending entirely through layer 24.
Referring to FIG. 3, a second SiO.sub.2 layer 30 is formed over silicon nitride layer 24 to fill pinholes 26. First and second silicon dioxide layers 22 and 30, together with silicon nitride layer 24, form dielectric layer 18. After formation of silicon dioxide layer 30, capacitor electrode 20 (FIG. 1) can be formed to complete construction of capacitor assembly 14 (FIG. 1).
It would be desirable to develop alternative methods of forming capacitor dielectric layers wherein one or both of oxide layers 22 and 30 is substantially eliminated.